Switching converters such as the buck converter shown in FIG. 1 are generally known in the current state of the art. Said converter comprises an MOS transistor 1 having a non-drivable terminal connected to an input voltage Vin and another non-drivable terminal connected to the cathode of an asynchronous rectifier diode D1 having its anode connected to ground GND; the transistor 1 is driven by a control device 2. The cathode of the diode D1 is connected to a low-pass filter comprising an inductor L and a capacitor C from whose ends the converter output voltage Vout is drawn.
In conditions of operation with the continuous conduction mode (CCM). that is when the current in the inductor L never goes to zero, and with a resistive type of load LOAD, if the transistor I has an “on” time Ton and an “off” time Toff, where T=Ton+Toff, it follows that Vout=D*Vin where D is the duty cycle given by D=Ton/T. In conditions of operation with the discontinuous conduction mode (DCM), that is when the current in the coil goes to zero during the switching period, the output voltage Vout is a function of the value of the inductor L, time period T, duty cycle D and input voltage Vin, i.e.,
  Vout  =            2      ⁢      Vin              1      +                        (                      1            +                                                            8                  ⁢                  L                                RT                            *                              1                                  D                  2                                                              )                2            where R is the resistive value of the load LOAD.
Another buck converter layout is shown in FIG. 2. The converter comprises a first MOS transistor HS having a non-drivable terminal connected to the input voltage Vin and another non-drivable terminal P connected to a terminal of the inductor L and a non-drivable terminal of a second MOS transistor LS connected to ground GND. The other terminal of the inductor L is connected to the capacitor C, having its other terminal connected to ground GND; the capacitor C is placed in parallel with the load LOAD and a resistive divider comprising a series of two resistors, R1 and R2. A fraction MFB of the output voltage Vout is input to a control device 20. The transistors HS and LS are switched on in a push-pull mode and as a result there is a lower power dissipation, given that the voltage drop across the transistor LS is lower than the voltage drop on the diode.
The control device 20 comprises a first circuit 24 comprising in turn an error amplifier 26 for comparing the voltage VFB with a reference voltage Vref and means able to effect a pulse width modulation (PWM) in response to said comparison. The control device 20 comprises two drive circuits or drivers 21 and 22 receiving as inputs the PWM signals output by the circuit 24 and able to drive the transistors HS and LS via the signals HSIDE and LSIDE. The driver 22 is powered by a voltage Vccdr whereas driver 21 is powered by a voltage Vcb originating from a bootstrap circuit 23 comprising a capacitor Cboot situated between the node P and the cathode of a diode Dcb having its anode connected to the voltage Vccdr.
When the converter is switched on, the node P is grounded GND and the capacitance Cboot is charged to the voltage Vccdr−Vd where Vd is the voltage drop of the diode Deb. When a pulse arrives from the PWM signal output by the circuit 24, the driver 21 starts to charge the gate of the transistor HS, supplying a charge Q drawn from the capacitance Cboot. When the transistor HS is switched on, the node P is brought to the voltage Vin and the voltage Vcb is forcibly brought to the voltage Vin+Vcboot where Vcboot is the voltage at the ends of the capacitor Cboot. In this condition the driver 21 supplies a voltage to the gate of the transistor HS that is sufficient to keep it on. The switching cycle concludes with the switching off of the transistor HS, whose gate is brought to the voltage of the node P. When the transistor LS is switched on, the node P is again brought to ground GND and the capacitance Cboot is thus recharged via the diode Dcb.
In order to prevent that in particular malfunction conditions the current carried by the transistors may rise to such a point as to damage or break them, overcurrent protection circuits are included in the regulators. There are a variety of devices able to implement overcurrent protection. Said devices include means capable of sensing the current that flows in the transistor or in the inductor L. Overcurrent protection is usually introduced in order to be able to guarantee a current limit even with switch-on times Ton shorter than the minimum time necessary for obtaining a reliable reading of the current in the transistor HS. Because of the noise due to parasite components and to the switching operations of the transistors, a masking interval (Tmask) is introduced in the current detection. Within this interval of time immediately after switching, no overcurrent is considered. It follows that in the case of switch-on times Ton shorter than Tmask any occurring overcurrent would be ignored, for this reason a reading of the current on the transistor LS is introduced.
When an overcurrent occurs there are various possibilities for intervention to avoid damage to the device or application.
One of said possibilities is to implement a protection device on the constant current, which once the threshold current IL_TH has been fixed, acts upon the circuit 24 in such a way as to maintain on the inductor a constant peak current equal to the value of the predefined threshold current.
The overcurrent protection in the constant current mode is implemented using a reading on the transistor HS or on both transistors, HS and LS. In the latter case, when an overcurrent is detected during the switch-off time Toff, the transistor LS is kept on for as long as said condition persists and the transistor HS is never switched on, as occurs with the device 27 of FIG. 2. This implies that no switch-on pulses will be considered for the transistor HS in order to guarantee the current limit. In such conditions it is possible to guarantee overcurrent protection between duty cycles of almost nil and duty cycles close to 100%.
Said type of protection may cause a loss of cycles and the converter may in such a case operate at a subharmonic frequency giving rise to a strong output ripple DIripple where
  DIripple  =                    Vin        -        Vout            L        ⁢          Tmask      .      In the case of large conversion ratios and a low value filter inductor, the converter may operate with a peak current ILpeak in the inductor exceeding the threshold current IL_TH and a lower working frequency, as is shown in FIG. 3.
In converters equipped with an overcurrent protection device like the ones previously described, at the end of the load transition that triggers said protection, an undesired over-elongation may occur in the output voltage Vout. In fact, during the action of the protection device, the output voltage Vout falls to a value below the regulation value and the error amplifier output saturates high, given that the feedback signal VFB is at a lower value than Vref. On coming out of said condition the converter will function with elevated duty cycles causing potential over-elongations of the output voltage Vout.